Office of microelectronics programs: programs, activities, and accomplishments

Nisr

National Institute of
Standards and Technology

Technology Administration

U.S. Department of Commerce

NISTIR 6707
January 2001

NATL INST. OF STAND & TECJ-

A 1 1 1 □ b 437D77

Electronics and Electrical
Engineering Laboratory

Office of

Microelectronics

Programs

Programs, Activities, and
Accomplishments^

U56

MO. 6707
2001

The Electronics and Electrical
Engineering Laboratory

Through its technical laboratory research programs, the Electronics and
Electrical Engineering Laboratory (EEEL) supports the U.S. electronics indus-
try, its suppliers, and its customers by providing measurement technology
needed to maintain and improve their competitive position. EEEL also pro-
vides support to the federal government as needed to improve efficiency in
technical operations, and cooperates with academia in the development and
use of measurement methods and scientific data.

EEEL consists of five programmatic divisions, two matrix-managed offices,
and a special unit concerned with magnetic metrology:

■ Electricity Division

■ Semiconductor Electronics Division

® Radio Frequency Technology Division

■ Electromagnetic Technology Division

■ Optoelectronics Division

■ Office of Microelectronics Programs

■ Office of Law Enforcement Standards

■ Magnetics Group

This document describes the technical programs of the Office of Microelec-
tronics Programs. Similar documents describing the other Divisions and
Offices are available. Contact NIST/EEEL, 100 Bureau Drive, MS 8100,
Gaithersburg, MD 20899-8100, Telephone: (301) 975-2220,

On the Web: www.eeel.nist.gov

Cover Caption: The National Semiconductor Metrology Program (NSMP) is
a NIST-wide effort desigend to meet the hightest priority measurement
needs of the semiconductor manufaturing industry and its supporting infra-
structure needs of the semicondutor manufacturing industry and its
supporting infrastructure industries. Research efforts include clean room
technology as it pertains to particle contamination and contamination free
manufatturing; rapid thermal processing (RTP) as shown in the RTP Ther-
mometry Test Bed Chamber for developing more accurate wafer
temperature measurement; and Nanometer-Scale Diminsional Metrolgoy with
Atomic Force Microscopy-a Calibrated Atomic Force Microscope image of a
specimen and tap lines on a SOI linewidth specimen. The line is ~500 nm
wide.

Electronics and Electrical
Engineering Laboratory

Office of

Microelectronics

Programs

Programs, Activities, and
Accomplishments

NISTIR 6707
January 2001

U.S. DEPARTMENT OF COMMERCE

Donald L. Evans, Secretary

Technology Administration

Karen H. Brown, Acting Under Secretary for Technology

National Institute of Standards and Technology

Karen H. Brown, Acting Director

Disclaimer: Certain commercial equipment and/or software are identified in this report to
adequately describe the experimental procedure. Such identification does not imply recom-
mendation or endorsement by the National Institute of Standards and Technology, nor does
it imply that the equipment and/or software identified is necessarily the best available for the
purpose.

References: References made to the International Technology Roadmap for Semiconduc-
tors (ITRS) apply to the most recent edition, dated 1999. This document is available from the
Semiconductor Industry Association (SIA), 181 Metro Drive, Suite 450, San Jose, CA 95110,
phone: (408) 436-6600, fax: (408) 436-6646.

Appendices: An index of researchers associated with the NIST-wide projects is located in
Appendix A. Appendix B contains a listing of all projects by Operating Unit. Appendix C is a
key to funding source acronyms.

Contents

Welcome v

Mission vi

Vision vi

Values vi

Goals vi

Office Organization vii

Task Areas

Critical Dimension and Overlay 11

Nanometer-Scale Dimensional Metrology with Atomic Force Microscopy

Scanning Electron Microscope Dimensional Metrology

Model-Based Linewidth Metrology

Linewidth Standards for Nanometer Metrology

Atom-Based Dimensional Metrology

Optical Overlay and CD Metrology

High Accuracy Two-Dimensional Metrology

Two- and Three-Dimensional Dopant Profiling 17

Scanning Probe Microscope Metrology

Thin-Film Profile Measurement Methods and Reference Materials

Thin-Film and Defect Characterization 19

Alternate Gate Dielectric Metrology for CMOS Technology
Thin-Film Process Metrology

Thin-Film Reference Materials and Measurements for Microelectronics
Compositional Metrology for Next Generation Gate Stack Materials
Ultra-Thin Dielectric Reliability Metrology

Chemical Characterization of Thin Films and Particle Contaminants
High-Resolution Microcalorimeter X-Ray Spectrometer for Chemical Analysis

Interconnect and Packaging. 23

Measurements for Electrodeposited Copper Interconnects
Interconnect Materials and Reliability Metrology

Test Structures for Mechanical Strain Characterization in IC Interconnects
Thin-Film Characterization from Transmission-line Measurement
Electron Beam Moire

Hygrothermal Expansion of Polymer Thin Films
Thermal Conductivity of Microelectronic Structures
Packing Studies (Wire Bonding to Cu/Low-K Semiconductor Devices
Solderability Measurements for Microelectronics

Wafer Characterization and Process Metrology 18

FTIR Methodology for Quantifying Oxygen in Heavily Doped Silicon

Wafer and Chuck Flatness and Thickness

Fundamental Process Contron Metrology for Gases

Low Concentration Humidity Standards

Plasma Process Measurements

Metrology for Contamination-Free Manufacturing

Temperature Sensing for Rapid Thermal Processing

Particle Measurements in Support of the Semiconductor Industry

Optical Scattering for Wafer Surface Metrology

Thermophysical Property Data for Modeling CVD Processes and

for the Calibration of Mass Flow Controllers

Lithography 23

Metrology for Deep Ultraviolet Lithography
Metrology for EUV Lithography

Modeling, Design, and Test 25

Metrology for Simulation and Computer-Aided Design
At-Speed Test of Digital Integrated Circuits

Appendices

Appendix A: Index of Researchers 28

Appendix Bs NIST-Wide Projects of the National Semiconductor

Metrology Program, FY 2000 29

Appendix C: Key to Funding Sources 31

Welcome

The Office of Microelectronics Programs provides coordination of silicon semiconductor
manufacturing metrology activities across NIST to maximize the impact of this critical indus-
try on the health of the U.S. economy. The Office, with a permanent staff of three, is located
in Gaithersburg, Maryland, and is one of the two Offices in the Electronics and Electrical En-
gineering Laboratory at NIST.

Many of the projects managed by the Office are cooperative activities across several Operat-
ing Units. Thus the projects are able to leverage the best expertise available for the specific
task across NIST, regardless of organizational structure. Our projects are also aligned by re-
search TASK area: Critical Dimension and Overlay; Two- and Three-Dimensional Dopant
Profiling; Thin Film and Defect Characterization; Interconnect and Packaging; Lithography;
and Modeling, Design and Test.

■ Additional activites of the Office which insure timely response to industry
needs include:

■ Extensive interactions with industry consortia, such as the Semiconduc-
tor Research Corporation (SRC) and International SEMATECH (ISMT).

■ Participation in the roadmapping activities commissioned by the Semi-
conductor Industry Association and administered by International
SEMATECH.

■ Standards bodies activities related to the semiconductor industry includ-
ing the Semiconductor Equipment and Materials International (SEMI)
standards program, American Society for Testing of Materials (ASTM) in
the US, and Deutsches Institut fur Normung (DIN) in Germany.

For additional information about the Office of Microelectronics Programs, please visit our web
site http://www.eeel.nist.gov/omp/

Vision

The Office of Microelectronics Programs will be recognized as an outstanding
organization managing and coordinating projects key to meeting the metrology needs of
the semiconductor manufacturing industry.

Values

The Office of Microelectronics Programs values relevance and focus of its projects in
solving crucial metrology issues facing the semiconductor manufacturing industry. The Office
values the technical excellence and the dedication of the scientists, engineers, and techni-
cians participating in the National Semiconductor Metrology Program.

Mission

The mission of the Office of Microelectronics Programs is to manage the National Semi-
conductor Metrology Program (NSMP), a NIST-wide effort designed to meet the highest
priority measurement needs of the semiconductor manufacturing industry and its supporting
infrastructure industries as expressed by the International Technology Roadmap for Semi-
conductors and other authoritative industry sources. The NSMP was established in 1994 with
a strong focus on mainstream silicon CMOS technology and an ultimate funding goal of
$25M. It is currently at $12M, with a broad portfolio of semiconductor metrology develop-
ment projects conducted in six of the Operating Units of the Measurements and Standards
Laboratories of NIST:

■ Electronics and Electrical Engineering Laboratory (EEEL)
ffl Manufacturing Engineering Laboratory (MEL)

■ Chemical Sciences and Technology Laboratory (CSTL)

■ Physics Laboratory (PL)

■ Materials Science and Engineering Laboratory (MSEL)

■ Building and Fire Research Laboratory (BFRL)

Goals

The Office of Microelectronics Programs will:

■ Diligently identify critical metrology gaps confronting the semiconductor
manufacturing industry, and implement robust projects to confront those
needs;

■ Insure expeditious technology transfer of NSMP results to the industry;
and

■ Assist the NIST technical body in interfacing efficiently with key elements
of the semiconductor manufacturing industry and its research and devel-
opment community.

I Engineering Laboratory

Office of Microelectronics Programs
Organization

(810.01)

2871 KNIGHT, Stephen, Director

4400 BUCKLEY, Michelle, Secretary

8125 MARTINEZ DE PINILLOS, Joaquin, V.,

Senior Scientist

5198 SCACE, Robert I. (GR/CTR)

2248 BELZER, Barbara J., Technical Staff Assistant (PT)

Legend:

CTR = Contractor
GL = Group Leader
GR = Guest Researcher
PD = Postdoctural
Appointment
PL = Project Leader
PT = Part Time
S = Student
ACT= Acting

Telphone numbers are:

(301) 975-XXXX, (the four
digit extension as indicated)

Permanent staff can generally
be contacted by email using
the following format:
firstname.lastname@nist.gov

Critical Dimension and Overlay

Task Goals

Advances in lithography have largely driven the
spectacular productivity improvements of the
integrated circuit industry, a steady quadrupling
of active components per chip every three years
over the past several decades. Lithography cur-
rently constitutes -35% of wafer processing
costs. The overall task of the Critical Dimension
and Overlay Program is to assist the industry in
providing the necessary metrology support for
current and future generations of lithography
technology. These goals include advances in
modeling, the provision of next generation criti-
cal dimension and overlay artifacts, and critical
comparisons of different critical dimension and
overlay measurement techniques.

Customer Needs

The 1999 International Technology Roadmap for
Semiconductors (1TRS) cites in Table 38 that the
five difficult challenges for the >100 nm node
(pre-2005) include resolution enhancement tech-
niques and post optical technique mask
fabrication, consensus among manufacturers for
the technology used, development of processes
to control minimum feature size to less than 7
nm, 3 sigma and development of new and im-
proved alignment and overlay control methods
independent of technology options. For the tech-
nology nodes < 100 nm, development of mask
process control methods is required to achieve
critical dimension, image placement, and defect
density acceptable in this regime. Also necessary
are the development of processes to control
minimum feature size to < 5 nm, 3 sigma and the
development of new alignment and overlay con-
trol methods independent of technology options.
Currently, resolution improvements have out-

paced overlay and CD measurement
improvements. It is believed that to keep costs
reasonable and production high, a total system
approach must be employed.

The industry needs to arrive at a consensus re-
garding the measurement technology that will be
used as the geometries continue to shrink. Refer-
ence materials traceable to NIST as well as
standards measurement methodology need to be
developed which address the continuing needs of
the industry.

Technical Strategy

Reference materials traceable to NIST and stan-
dard measurement methodologies require that
NIST develop a clear understanding of the un-
certainties associated with in-line critical
dimension measurements. Evidence exists that
by combining the strengths of SEM (excellent
lateral information) and SPM (excellent height
information), a significant reduction in meas-
urement uncertainties can be achieved.

Development of a metrology such as a calibrated
Atomic Force Microscope (AFM) and devising
both a calibration service and a Standard Refer-
ence Material (SRM) will support tool matching
requirements in industry fabrication facilities.

NIST continues to work toward ensuring fully
automatic size and shape measurements of 3-
dimensional features < 180 nm that are com-
pleted in seconds with an accuracy and precision
approaching atomic levels. Collaborative and
cooperative interactions with industrial partners,
both domestic and international, will assist
reaching these goals and establishing traceability
to NIST.

Projects

Nanometer-Scale Dimensional
Metrology with SEM and Scanned
Probe Techniques

Nanometer-Scale Dimensional
Metrology and Atomic Force
Microscopy

OU: MEL

Researchers: John Dagata

Michael Postek

Funding Sources: NIST OMP (50%)

Other Agency (50%)

" Improve measurement uncertainty of SEM
CD measurements by modeling of intensity pro-
files required to obtain reliable estimates of step
heights;

■ Utilize the NIST built combined SEM and
SFM instrument to test the feasibility of a two-
method approach;

■ Partner with a university to develop software
permitting 3-D image reconstruction.

OU: MEL

Researchers: Ronald G. Dixon

Theodore Vorburger

Funding Sources: NIST OMP (26%)

NIST STRS (51%)

NIST ATP (15%)

Other Agency (8%)

■ Develop of Calibrated AFM (C-AFM) de-
signed to aid the development of AFM
standards;

■ Conduct an industrial round robin and im-
prove uncertainty levels of 1.5 nm at the sub-
micron level;

B Continue development of SRM 2089 for re-
lease in 2002.

polysilicon gate J

/ gate ^

oxide /

/ /

/ silicon substrate /

MGS capacitor

Calibrated AFM

Comparison of the topographical and electrical
homogeneity of a polysilicon gate using atomic
force microscopy (AFM) and Scanning Maxwell-
Stress Microscopy (SMM)

Scanning Electron Microscope
Dimensional Metrology

Model-Based Linewidth
Metrology

OU: MEL

Researchers: John S. Villarrubia

Andras Vladar
Michael Postek

Funding Sources: NIST OMP (50%)

Other Agency (50%)

“ Cooperative interaction among practitioners
of various techniques sharing information with
the goal of improving linewidth measurement
capabilities within NIST and the Semiconductor
Industry;

* Develop competence sufficient to calibrate
an industrially relevant wafer linewidth standard;

■ Transfer improved measurement methodol-
ogy developed at NIST to industry

OU: MEL

Researchers: Michael Postek

Funding Sources: NIST OMP (25%)

Other Agency (75%)

■ Develop standard artifacts for processes at
150 nm and below;

■ Issue SRM 2091;

■ Evaluate procedure for correctly measuring
image sharpness collaboratively with Interna-
tional SEMATECH.

Cross-sectional view of a resist line overlaid
with the structure calculated from top-down view
of the line by Adaptive Monte Carlo Modeling

Atomic force microscope image of a single
crystal critical dimension artifact

Linewidth Standards for Nanometer
Metrology

OU: EEEL

Researchers: Michael W. Cresswell

Richard A. Allen

Funding Sources: NIST OMP (99%)

Other Agency (1%)

a Develop test-structure-based electrical me-
trology methods and related reference materials
that have the primary emphasis on linewidth
metrology and calibration.

B Develop a traceability pathway for dimen-
sional certification provided by HRTEM
imaging and a secondary reference using sub-
nanometer repeatability of electrical CD
metrology.

Atom-Based Dimensional
Metrology

OU: MEL

Researchers: Richard M. Silver

Funding Sources: NIST OMP (20%)

NIST STRS (25%)

Other Agency (55%)

■ Develop 3-Dimensional structures of con-
trolled geometry whose dimensions can be traced
directly to intrinsic crystal lattice;

■ Develop methods to prepare photo-
lithographically patterned 3-D structures in Si
and GaAs. Structures must be prepared in such
materials as to allow the atomic surface recon-
struction of those features such that the atomic
order is commensurate with the underlying
crystal lattice. This fabrication is to occur at In-
ternational SEMATECH.

-Tip

A- Image

Sample

VjWAWW'A»’iAi’iA

Lattice-plane selective etches provide reference
features with atomically planar sidewalls

Vacuum atomic force microscope image of lattice
steps in silicon

Optical Overlay and
CD Metrology

OU: MEL

Researchers: James Potzick

Richard Silver

Funding Sources: NIST OMP (50%)

Other Agency (50%)

■ Develop instrumentation and overlay me-
trology methodology for optical overlay CD
measurements;

■ Design and calibrate standard artifacts for
optical overlay and CD metrology;

■ Develop microlithography process modeling
for the improvement of photomask metrology to
improve its effectiveness through exposure
emulation, making the needed tools readily
available to customers and easy to use;

■ Develop an open framework for snap-
together microlithography process simulation
products from diverse suppliers, which together
model the specifications-to-wafer process;

■ Simulate, under intended exposure and de-
velopment conditions, photomask performance
based mask design and on mask measurements;

■ Link existing and new simulation products
through dialog and consensus among a group of
leading suppliers and users of process modeling
software and related metrology tools.

High Accuracy Two-Dimensional
Metrology

OU: MEL

Researchers: Ted Doiron

Richard Silver

Funding Sources: NIST OMP (100%)

■ Develop an artifact standard that can be used
to bring all the 2-Dimensional based inspection
instruments to the same metric;

■ Develop an industry consensus standard
grid, measure by the state-of-the-art measuring
machines in private industry, and verify the
measurements using NIST capabilities;

■ Develop an artifact standard that can be used
to bring all the 2-D based inspection instruments
to the same metric.

Significant Accomplishments

H In cooperation with a researcher at the Uni-
versity of Tennessee-Knoxville, we have
demonstrated that nano-tips used in high-
resolution scanning electron microscopes can
significantly improve the signal to noise over re-
sults achievable with conventional field emission
tips.

■ A process has been developed that allows
for renewal of nano-tips for field emission elec-
tron guns used in ultra-high resolution scanning
electron microscopy.

■ In the course of measuring linewidth on sin-
gle-crystal artifacts, researchers have determined
that SEMs have extraordinary sensitivity to tilt.
This allows the development of highly repro-
ducible orientation references, for example, on
an SEM’s sample positioning stage.

* New image recognition and quantitative im-
age analysis software has been developed which
allows the evaluation of numerous effects on al-
gorithm performance to quantify feature
roughness and asymmetry effects on an overlay
pattern. The code has been used extensively to
evaluate and compare several cross-correlation,
auto-correlation, and new least-squares correla-
tion methods.

■ A silicon-wafer carrier has been developed
that mimics the appearance of a product wafer to
metrology systems. The artifact incorporates ex-
act orthogonality of the recessed pit containing
the test chip, flatness of the pit floor, control of
the lateral dimensions of the pit, and pit sidewall
slopes crystallographically defined at 54.37 de-
grees. Technology transfer to a commercial
collaborator has resulted in the production of a
prototype in wafer sizes commensurate with cur-
rent manufacturing capabilities.

■ The process collaboratively developed at
Sandia National Laboratories by NIST and San-

dia researchers that has been used to make the
prototype single-crystal CD reference materials
is being transferred to VLSI Standards, Inc.
VLSI Standards is evaluating the prospects of
producing CD reference materials based on this
technology.

■ The work of the Semiconductor and Materi-
als International (SEMI) Standards task force on
metrology terms and definitions has become the
industry standards SEMI P35-0200, "Terminol-
ogy for Microlithography Metrology." To
coordinate semiconductor metrology terms with
usage in other industries, this standard contains
definitions from the International Organization
for Standardization (ISO) “International Vo-
cabulary of Basic and General Terms in
Metrology”, reference to the ISO "Guide to the
Expression of Uncertainty in Measurement", and
terms describing some new concepts in the
measurement of microscopic feature size of
linewidth.

■ developed an instrument in-house, capable
of performing concurrent scanned probe micro-
scope- (SPM) based nanolithography,
dimensional and electrical characterization by
scanning Maxwell-stress microscopy (SMM),
and traditional device probing has been demon-
strated using a silicon lateral-tunneling Silicon
On Insulator (SOI) device test structure.

■ A NIST researcher, working with collabo-
rators in Japan and Taiwan, has achieved
significant improvements in the performance and
sensitivity of electric force microscopy for
nanoelectronic device characterization.

* NIST and the Physikalish-Technische Bun-
desanstalt (PTB) completed a set of
measurements on a prototype two-dimensional
grid. This same plate was measured at several
industrial sites as well, and is a critical link in the
international traceability chain.

Two- and Three-Dimensional
Dopant Profiling

Task Goals

The dimensions of the active transistor areas are
approaching the spacing between dopant atoms,
complicating both modeling and doping gradient
measurements. The overall task of these projects
is to provide suitable metrology for this stochas-
tic regime.

Customer Needs

In 1999, the ITRS expresses the desired spatial
resolution of 3 nm and precision in concentration
of ±5%. By 2005, resolution of 1 .5 nm and ± 3%
precision in at-line dopant concentration is pro-
posed. Scanning Capacitance Microscopy (SCM)
has emerged as a leading contender to provide
2-D carrier profiles. SIMS is most likely to pro-
vide the solution to precision requirements for
dopant concentration measurements. Relatively
accurate profiles of the dopant concentration can
by obtained when SCM images are combined
with SIMS measurements.

Technical Strategy

At the device dimensions projected, the ability
for those devices to work depends strongly on
the carrier concentrations throughout the mate-
rial. It is therefore essential that techniques and
methodologies are developed which can support
these needs and that reference materials and
standards are made available for calibration of
the in-line tools.

The two projects in this area share a goal to de-
velop physical models based on their research
results and proved interpretation formalisms for
the images and measurements obtained.

Researchers are developing depth profiling refer-
ence materials and reference materials for
Scanning Capacitance Microscopes (SCMs) in
addition to providing 2-D carrier profiles using
SCM and developing 3-D physical models.
There is also significant development in devising
measurement methodologies for the depth pro-
filing techniques using Secondary Ion Mass
Spectrometry (SIMS) with ion sources unique to
NIST.

Projects

Scanning-Probe Microscope Metrology

OU: EEEL

Researchers: Joseph J. Kopanksi

Brian G. Rennex
Jay. F. Marchiando

Funding Sources: NIST OMP (100%)

■ Develop measurement methodology, physi-
cally based models, and interpretation
formalisms to make Scanning Capacitance Mi-
croscopy a practical metrology for 2-D carrier
profiling of silicon;

■ Develop 2-D and 3-D finite element solu-
tions of Poisson's equation for the SCM
geometry and transfer this capability to industry
through NIST developed software, FASTC2D.

SCM image of a p+ln junction

UOIIISOJ A

Dopant contours extracted with FASTC2D

Thln-Film Profile Measurement
Methods and Reference Materials

OU: CSTL

Researchers: David S. Simons

Greg Gillen

Funding Sources: NIST OMP (100%)

B Improve the capabilities for compositional
depth profiling to support the semiconductor in-
dustry;

H Define optimum procedures for ultra-high
depth resolution and ultra-shallow profiling by
SIMS;

H Develop depth-profiling reference materials
needed by the semiconductor industry;

B Develop methods to improve uncertainty of
implant dose measurement by SIMS (Interna-
tional SEMATECH collaboration).

Significant Accomplishments

H FASTC2D version 1 software code was
completed and distributed to the 40-member
SEMATECH working group on 2-D profiling.
User feedback and comments were incorporated
into the code.

■ Collaboration began with Los Alamos Na-
tional Laboratories (LANL) to use their LaGriT
(Los Alamos Gridding Toolkit) software as a li-
brary of user-callable tools. Jay Marchiando
spent a 3-month sabbatical during the summer of
2000 at LANL learning to use and apply LaGriT.

m Interaction initiated with Howard Univer-
sity, Washington, D.C., to apply SCM to high
bandgap semiconductors. A senior engineering
student has taken on a project to make a prelimi-
nary study of SCM in applying it to silicon
carbide as her senior project.

■ A project was initiated with International
SEMATECH (ISMT) to study improved meth-
ods for depth profiling of thin Zr02 gate
dielectric materials. Depth profiles conducted
with the NIST prototype SL5+ primary ion source
demonstrated superior depth resolution and
minimal artifacts as compared to SIMS depth
profiling with more conventional Cs+ or 0;+
primary ion beams.

Ion Source

Thin-Film and Defect Characterization

Task Goals

As device dimensions continue to shrink, critical
films approach the realm of several atoms thick,
challenging thickness and roughness metrology
as well as electrical and reliability characteris-
tics. The gate dielectric, traditionally SiCT, will
soon no longer be viable. The overall task is to
provide suitable metrology and reference materi-
als for thin dielectrics and conducting barrier
films, including electrical characterization,
thickness and roughness metrology, and reliabil-
ity metrology.

Customer Needs

The 1999 ITRS indicates near that in the near
term, 2003-2005, equivalent gate dielectric
thickness needs to be ~ 1.5 nm with process tol-
erance of ± 4% (3 a). The reliability of SiOi at
this thickness level is not sufficient. The physics
of failure and traditional reliability techniques
must be reexamined for ultrathin dielectrics that
exhibit excessive tunneling current and soft
breakdown. There is a need for refining electrical
and reliability characterization methodologies,
establishing standard reference data, and devel-
oping a fundamental understanding of the
relationship between gate dielectric material and
device electrical measurement.

Spectroscopic Ellipsometry (SE) is a preferred
measurement method for process monitoring, as
it is non-invasive, non-destructive, and is rela-
tively quick. In addition to on-line and at-line
measurements accurately determining thickness
of gate dielectrics, SE is shown to make signifi-
cant contributions toward the development of
techniques to determine the structure of the films
and their interfaces. Improvements must be made
in the understanding between physical, electrical,
and optical determination of film properties. Re-
search is needed to link these methods together
and provide models, data, and standards for
transferring the information to the industry.

Other research areas are needed that investigate
techniques minimizing material dependent cali-
bration requirements for in-line tools. There is
currently a comprehensive effort at NIST using
x-ray measurement methods.

Future gate dielectrics pose problems in chemi-
cal status and layer thickness determination of <
8 nm. A need exists not only for improvements

in measurement accuracy and refinement in
available measurement technologies, but im-
provements in the data used to analyze silicon
and the dielectrics grown upon it.

Technical Strategy

Seven interrelated and often complementary
projects offer a diverse approach to arriving at
practical solutions to thin film characterization
needs. The pace of development demands crea-
tive solutions for devising practical mechanisms
for measurements that are traceable to NIST in-
cluding Standards Reference Materials (SRMs).
NIST Traceable Reference Materials (NTRMs).
and Standard Reference Data (SRD). We are in-
volved in a collaboration to extend
characterization schemes developed on thin ox-
ide and oxide-nitride gate dielectrics to the newer
metal oxides and silicate dielectrics.

Much of the characterization is tied to the reli-
ability effort. The physical mechanisms
responsible for “soft” or "quasi” breakdown
modes in ultra-thin SiO: films and its implica-
tions for device reliability are being investigated
as a function of test conditions and temperature.
Tests are used to determine the thermal and
electrical acceleration parameters of device
breakdown. Our efforts include providing insight
to the physical mechanisms of ultra-thin gate
oxide wear-out and breakdowns. We are apply-
ing electrical measurement techniques,
procedures, and analysis.

Determining the electrical and physical proper-
ties of thin oxide and alternate gate dielectrics
require that we relate optical, electrical, and
physical measurements of thickness. Our ap-
proach is collaborative involving key researchers
at NIST, International SEMATECH, SRC uni-
versity staff, and integrated circuit (IC) industry
personnel. NIST regularly leads and participates
in multi-method test studies.

Concurrently, we continue to provide support for
thin film calibration standards and methodology
developing a mechanism to enable traceability to
NIST by suppliers of secondary thin-film refer-
ence materials.

Optical methods employed include spectroscopic
ellipsometry using an instrument and software
developed at NIST to provide structural and op-
tical models. High-resolution x-ray diffraction

techniques and advanced modeling methods have
also been developed to a high degree of sophisti-
cation in-house. X-ray probes and measurement
methods are also used to characterize thin-films
and their microstructures.

A new technique, Grazing Incidence X-ray Pho-
toelectron Spectroscopy (GIXPS), was
developed and is shown to obtain both thickness
and chemical state information of thin films.
These measurements are correlated where possi-
ble witli ellipsometry, AFM, and X-ray
reflectometry.

Projects

Alternate Gate Dielectric Metrology for
CMOS Technology

OU: EEEL

Researchers: Eric Vogel

Funding Sources: NIST OMP (62%)

1ST SRD (38%)

■ Develop standards, techniques and data for
comparison and development of alternate gate
dielectrics;

H Obtain device samples and blanket films
from other industry and university groups, elec-
trically characterize devices, collaborate with
other researchers on analytical characterization;

* Assess, modify and standardize electrical
characterization methodologies and data for de-
vices with ultra-thin oxide and oxide-nitride
dielectrics;

■ Provide standard electrical and reliability
measurements, standard electrical data and im-
proved fundamental understanding of electrical
properties associated with metal oxide and sili-
cate dielectrics.

Fraquaxy (Hz)

Experimental and modeled interface state
conductance for a tunneling gate dielectric

Thin-Film Process Metrology

OU: EEEL

Researchers: James R. Ehrstein

Curt A. Richter
Nhan V. Nguyen

Funding Sources: NIST OMP (84%)

NIST: (10%)

Other Agency (6%)

■ Focus on relating optical, electrical, and
physical measurements of thickness, composi-
tion, and interface structure and developing and
providing the basis for traceability to NIST for
film thickness measurements;

■ Identify structural models and develop pre-
ferred optical index dispersion models or data for
improved ellipsometric analysis of future gen-
eration gate dielectric film systems;

■ Identify preferred software and use to im-
prove correlation between electrical and
ellipsometric methods;

■ Transfer to first level commercial suppliers
of reference materials traceability to NIST down
to 2 nm for oxide films;

■ Distribute software to International
SEMATECH and collaborating universities for
evaluation.

Bias Voltage (V)

Metrology' for Thin Oxide and Alternate Gate Dielectrics

Spectroscopic Ellipsometry and Analytical Characterization of Gate Dielectrics
100

8.0
o.o

40

Rapid 20
Determination 00
Amorphous or 80
Polycrystal

Phase of Ta,Os 8 0

w 40
2.0

0.0

18 20 2.6 30 3.5 40 48 50 6 5 00

ev

• Optical properties and traceable reference data, matenals, and measurements

• Cross correlation of analytical techniques for composition and thickness

• Benchmarking of device simulators including quantum mechanical effects and
polysilicon depletion

X-Ray Measurement Methods for
Characterization of Thin Films and
Their Microstructures

OU: PL

Researchers: Richard Deslattes

Richard Matyi

Funding Sources: NIST OMP(20%)

NIST STRS (50%)

Cost Recovery (30%)

■ Provide an accurate system of measurements
for structural parameters of semiconductor thin-
film and multiplayer systems. These techniques
need to be non-destructive, non-invasive, and
give results robustly connected to the SI.

Detail of Grazing Incidence X-ray Reflectometer

Compositional Metrology for Next
Generation Gate Stack Materials

OU: STL

SEL

Researchers: John A Small

Debra Kaiser

Funding Sources: NIST OIMP (100%)

■ Develop an approach to fabricate BST thin-
film reference standards.

Ultra-Thin Dielectric Reliability
Metrology

OU: EEEL

Researchers: John S. Suehle

Eric Vogel

Funding Sources: NIST (100%)

Model and data for combined effects of substrate
hot-electron injection and high voltage stress on
the lifetime of ultra-thin gate oxides

■ Develop and evaluate methods, tools, diag-
nostic procedures, and physical models for

understanding and improving the reliability of
ultra-thin Si02 and alternate gate dielectrics;

■ Develop and evaluate methods, tools, diag-
nostic procedures, and physical models for

understanding and improving the reliability of
metal interconnects such as copper;

■ Develop new standard voltage stress test for
time dependent dielectric breakdown.

Dr. John Suehle preparing to load a sample on
wafer prober

Chemical Characterization of Thin
Films and Particle Contaminants

OU: CSTL

Researchers: John A. Small

Eric Steel

Funding Sources: NIST OMP (100%)

0 Measure sets of well-prepared thin-film in-
sulator samples that will highlight discrepancies
between well-established techniques;

® Arrive at corrections that can be applied to
each technique to give them absolute sub-
nanometer accuracy between 1 nm and 8 nm;

■ Develop analysis methods to improve accu-
racy of analysis for particles less that 100 nm in
size;

■ Develop analytical standards in support of
these measurements;

■ Improve beamline optics for GIXPS;

B Develop small angle cleavage technique;

■ Improve precision on Si (O, N)x (Sematech
providing some samples)

High-Resolutsor? Microcalorimeter
X-Ray Spectrometer for Chemical
Analysis

OU: EEL

Researchers: David Wollman

John Martinis
Gene Hilton
Kent Irwin

Funding Sources: NIST OMP (50%)

Other Agency (50%)

■ Improve x-ray spectrometer system for par-
ticle analysis using the unique low-noise, high
sensitivity properties of cryogenic electronics;

■ Specifically addresses need for improved
particle analysis.

Significant Accomplishments

H Demonstration that a Tauc-Lorentz disper-
sion is the preferred optical model for candidate
gate dielectric materials titanium-dioxide and
tantalum pentoxide; demonstration of limit for
use of a single Tauc-Lorentz oscillator at about

1 eV above the optical gap, and demonstration of
the ability of spectroscopic ellipsometric char-
acterization to show formation of crystalline
phases as a result of processing temperatures.

■ Benchmarking-comparisons of five leading
university- and industry-developed advanced
quantum mechanical modeling programs showed

that quantitative differences among the programs
in the gate dielectric thickness values they would
extract from C-V data are significant compared
to levels needed for manufacturing control as
outlined in the ITRS.

® A study was conducted investigating the
temperature dependence of time-dependent di-
electric breakdown in sub-3 nm Si02 films. The
results indicate that soft and hard breakdown
modes exhibit the same thermal acceleration and
that the thermal activation energy is observed to
decrease for higher gate voltages. The work ex-
plains conflicting data trends that have been
reported in the literature.

■ New work studied the effect of stress inter-
ruption on the lifetime of ultra-thin gate oxides.
Experiments were conducted to study the effect
of periodically interrupting stress to monitor the
increase in low-voltage leakage current in ultra-
thin oxides, a popular technique for detecting
breakdown in ultra-thin oxides. The results show
that stress interruption longer than Is does not
affect the defect generation and TDDB life dis-
tributions.

■ Substrate hot hole injection studies of ultra-
thin oxide show that defect generation caused by
holes has extremely weak temperature depend-
ence. Furthermore, the results show an oxide can
withstand more defects created by holes than
created by electrons. The results shed doubt on
the current anode hole injection theory for de-
scribing oxide breakdown.

■ Numerous studies were performed to inves-
tigate the reliability of oxide/nitride stacks.
Preliminary results indicate the importance of
N20 annealing to reduce the defect generation
rate and improve the Weibul slope. The results
suggest that an oxide/nitride stack with N20 an-
neal has better reliability than an oxide at the
same equivalent oxide thickness.

■ Initial measurements of the energy distribu-
tion of the interface state density of Zr02/Si02
and Zr02/Si3N4 are much higher than pure Si02.
However, the time constant (capture cross sec-
tion) of these defects are identical to that of Si02
suggesting a similar physical nature (i.e. Pb
center, silicon dangling bond).

“ The hardware, software, and analysis rou-
tines for performing 3-level and sinusoidal
charge pumping were set up. Defect densities of
oxide-nitride stacks were measured and ana-
lyzed.

Interconnect and Packaging

Task Goals

Advances in interconnect and packaging tech-
nologies have introduced rapid successions of
new materials and processes. Environmental
pressures are leading to the reduction and even-
tual elimination of lead in solder used for
attaching chips to packages and packages to cir-
cuit boards. The overall task of this program is to
provide critical metrology and methodology for
mechanical, chemical, metallurgical, electrical,
thermal, and reliability evaluations of intercon-
nect and packaging technologies.

Customer Needs

The function of interconnect is to distribute sig-
nals and to provide power and ground to and
among the various components on the integrated
circuit. The challenges for > 100 nm (pre-2005)
include new materials and processes to meet re-
sistivity and low-/high-K dielectrics. The
continuing shrinking of critical dimensions,
driving up the impedance of long interconnect
lines, and the need to reduce costs, is forcing the
rapid introduction of copper with barrier materi-
als and 1ow-k dielectrics. Beyond 2005, for the <
100 nm technology node, dimensional control
and metrology become all the more critical. So-
lutions beyond copper and 1ow-k materials must
be found.

The function of packaging is to connect the inte-
grated circuit to the system or subsystem
platform, such as circuit board, and to protect the
integrated circuit from the environment. The in-
creasing number of input/output (I/O)
connections on circuits with a vastly larger scale
of integration is forcing ever smaller I/O pitches,
the use of flip-chip bonding, and the use of in-
termediary platforms called interposers. The
integration of sensors and actuators onto inte-
grated circuits through Microelectromechanical
Systems (MEMS) technology and the increasing
use of low cost integrated circuits in harsh envi-
ronments is increasing the complexity of the
packaging task. Environmental concerns are
forcing the need for development of reliable
lead-free solder and other low-environmental-
impact packaging materials.

System reliability requirements demand model-
ing, testing methods, and failure analysis of the
integrated circuits before and after packaging.
Metrology is a significant component of reliabil-
ity evaluation.

Technical Strategy

We are providing fundamental measurements on
the chemistry of the generic copper plating proc-
ess, allowing industry to optimize the process for
deposition of narrow high-aspect-ratio copper
interconnect structures.

In collaboration with industry, we are developing
and refining a robust suite of test structures,
methods, and diagnostic procedures to evaluate
the mechanical and environmental properties and
reliability of interconnect and packaging struc-
tures. By applying complementary approaches,
specific issues are being addressed.

Both miniaturized conventional tensile testers
and CMOS-compatible MEMS test structures are
being developed to evaluate the mechanical
properties of the individual components and the
composite structures in interconnect systems.

The conductance and capacitance of transmission
line test structures are measured over a wide fre-
quency range to evaluate alternative dielectrics
and to permit modeling of the frequency charac-
teristics of interconnect structures.

A high sensitivity capacitance cell has been de-
veloped to evaluate the dimensional stability of
polymers used in packaging, and a micro-scale
thermal conductance method is being developed
to permit measurement of the thermal character-
istics of packages. Electron-beam Moire is used
to observe deformations in package structures,
allowing modeling of micro-scale thermo-hygro-
mechanical behavior.

Working with industrial partners, we are devel-
oping evaluation techniques for bonding
systems, both for wire to chip with emphasis on
the new copper/low-K interconnect, and package
to board, with emphasis on lead-free solders.

Projects

Measurements for Electrodeposited
Copper Interconnects

OU: MSEL

Researchers: Gery R. Stafford

Mark Vaudin

Funding Sources: NIST OMP (40%)

NIST STRS (60%)

8 Provide better understanding of the mecha-
nism by which organic reagents inhibit copper
deposition reaction;

■ Understand mechanism of factors control-
ling copper recrystallization behavior of Cu
electrodeposits;

■ Determine recrystal lization kinetics of cop-
per films as a function of deposition current
density and film thickness.

0 2.5 5.0 7.5 10. i) 12.5

A 13 x 13 nm STM image of (V2 x V2)R45°
chlorine adlattice on Cu(lOQ) at -0.169 V vs.
Cu/Cu+ in 10 mmol/l HCI

Interconnect Materials and Reliability
Metrology

OU: EEEL, MSEL

Researchers: Harry Schafft

David Read
Fred R. Fickett
Robert R. Keller
Chrristine E. Kalnas
John E. Bonevich

Funding Sources: NIST (100%)

■ Evaluate test structure designs and test
methods for characterizing copper interconnects;

■ Design and submit to MOSIS a test structure
for tensile testing of metal interconnect layers;

■ Measure crystal distortions in copper speci-
mens with extrapolation to interconnect stress
and strain states.

TEM electron diffraction pattern of interconnect
metallization crystallite

Test Structures for Mechanical Strain
Characterization in Integrated Circuit
Interconnects

OU: EEEL

Researchers: Michael Gaitan

Funding Sources: NIST OMP (19%)

NIST STRS (57%)

ATP (24%)

■ Provide domestic industry with MEMS-
based test structures and standardized test meth-
ods for characterizing the thermo-electro-
mechanical properties of thin films used in inte-
grated circuits suitable for in-line metrology;

■ Develop test method for elastic modulus in
IC interconnects to derive the mechanical stress
of interconnects.

Fixed-fixed beam test structure array for
measurement of mechanical strain and
interconnects in multilayer structures

Thin-Film Characterization from
Transmission-line measurement

OU: EEEL

Researchers: Dylan F. Williams

Michael Janezic

Funding Sources: NIST OMP (100%)

a Develop methods to accurately measure the
dielectric properties of 1ow-k thin films from in-
situ transmission-line measurements.

Small printed transmission line

Thin-film permittivity from microstrip test
structures

Electron Beam Moire

OU: MSEL

Researchers: Elizabeth Drexler

David Read

Funding Sources: NIST OMP (50%)

NIST STRS (50%)

H Develop and apply Moire techniques to the
measurement of strain and observation at high
magnification;

H Assess new method for making Moire grat-
ings with the goal of sub-25 nm pitches;

0 Apply electron beam Moire to measure dis-
placements at a suspected interfacial flaw
identified by thermal microscopy.

Thermal Conductivity of
Microelectronic Structures

OU: MSEL

Researchers: David R. Smith

Funding Sources: NIST OMP (25%)

NIST STRS (75%)

■ Demonstrate advanced methods of meas-
urement of thermal effects within packaging
structures and their components;

H Develop measurement methods for absolute
thermal conductivity of interconnect structures at
the micron scale

■ Demonstrate quantitative application of in-
frared microscopy to thermal transport
measurement and detection of incipient failure in
microelectronic packages.

Hygrothermal Expansion Of Polymer Thermal image of package structure

Thin Films

OU: MSEL

Researchers: Chad R. Snyder

Funding Sources: NIST OMP (100%)

® Measure the changes with temperature and
humidity of the out-of-plane dimensions on
polymer thin films;

H Complete and test new capacitance cell and
make available to industrial users.

Capacitance cell

ical Engineering Laboratory

Packaging Studies (Wire Bonding to
Cu/Low-k Semiconductor Devices)

OU: EEEL, MSEL

Researchers: George Elarmon

David Kelley
Chris Johnson

Funding Sources: NIST OMP (60%)

NSIT STRS (40%)

■ Develop the best/most economical practical
bonding surfaces/subsurface support structures
and techniques for wire bonding to advanced
semiconductor devices with Cu metallization;

■ Resolve diffusion issues that relate to these
interfaces;

■ Determine diffusion coefficients of Cu into
Au using metal films deposited in the same man-
ner as on Cu-conductor chips and evaluate the
results with actual wire bonding experts.

Scanning electron micrograph of tine-wire
wire bonds

Soiderability Measurements for
Microelectronics

OU: MSEL

Researchers: Frank Gayle

Gery R. Stafford

Funding Sources: NIST OMP (100%)

■ Improve soiderability test methods, includ-
ing new lead-free solders;

a Facilitate high-temperature-fatigue-resistant-
solder consortium.

Significant Accomplishments

Filed a patent on (NIST Docket #00-018US) en-
titled: "Inorganic Non-Metallic, Wire

Bondable Top Surface Coating For Use In
Wire Bonding To Copper Metallization On
Semiconductor Chips "

Researchers successfully completed the Hy-
grothermal Expansion of Polymer Thin Films
project. Drawings of the capacitance cell are
available for transfer to the industry.

Cross-section of soldered lead

Wafer Characterization and
Process Metrology

Task Goals

Device scaling has been the primary means by
which the semiconductor industry has achieved
the unprecedented gains in productivity and per-
formance quantified by Moore’s Law. With the
replacement of the traditional silicon dioxide/
polysilicon gate stack processes with materials
capable of supporting ever shrinking geometries,
the task of the industry becomes more difficult.
The overall task represented by the projects be-
low reflects the need for analytical techniques
with unparalleled accuracy, robustness and ease
of use.

Customer Needs

Continued reduction in transistor dimensions
demand tighter control of silicon substrate flat-
ness, dopant and oxygen content, and surface ion
and particle contamination. Tighter process con-
trol is required to fabricate the intricate
transistor, passive component and interconnect
structures.

Technical Strategy

A broad suite of wafer characterization metrol-
ogy tools and methods are being developed and
used to address industry needs for wafer flatness,
particle contamination and identification, and
doping level monitoring. A wide range of proc-
ess metrology development, fundamental
properties, measurement services, and reference
materials are under development. Both destruc-
tive and nondestructive techniques are being
investigated, with emphasis on the later for in-
line and at-line metrology.

A variety of optical techniques are being devel-
oped to provide metrology for both wafer
geometry and oxygen content. The goal is to
provide full wafer characterization non-
destructively.

Accurate metrology of process gases is essential
for reproducible manufacture of semiconductor
products. Critical physical parameters are being
measured on a wide variety of reactive and non-
reactive process gases, allowing the accurate
calibration of How meters and residual gas ana-
lyzers. Water contamination at extremely low
levels in process gases presents serious manu-
facturing difficulties; a low water vapor pressure
calibration facility has been developed and is

being used by industry for calibration of water
vapor sensors.

A wide variety of metrology issues emerge in
plasma, chemical vapor, and rapid thermal proc-
essing steps used in semiconductor manufacture.
A number of projects are addressing contact-less
thermometry, particle formation, and plasma di-
agnostics with an emphasis on real time control.

Detection and accurate sizing of particle con-
tamination continues to challenge semiconductor
manufacturing. Methods for rapid detection as
well as polystyrene latex spheres for calibration
standards are under development.

Projects

FTTR Methodology for Quantifying
Oxygen in Heavily Doped Silicon

OU: EEEL, CSTL

Researchers: Deane Chandler-Horowitz

James E. Maslar

Funding Sources: NIST OMP (100%)

■ Develop FTIR methodology for measuring
interstitial oxygen in conducting silicon wafers.

0 55

0 50

0 45

2 0 40

§ 0 35
c
CO

■t 0 30
0 25

0 20

0 1000 2000 3000 4000

photon energy (cm )

Wafer and Chuck Flatness and
Thickness

OU: MEL

Researchers: Christopher Evans

Angela Davies
E. Clayton Teague

Funding Sources: NIST OMP (100%)

■ Develop full aperture interferometric meth-
ods to evaluate important wafer characteristics
such as flatness, thickness, thickness variation,
and bow.

Preliminary evaluation of high spatial frequency
noise of 0.037 nm rms

Fundamental Process Control
Metrology for Gases

OU: CSTL

Researchers: Robert Berg

Funding Sources: NIST OMP (100%)

■ Develop primary flow standards in the flow
range for 10 7 mol/s to 10 7 mol/s and transfer
these capabilities to the semiconductor industry;

■ Support process control with improved RGA
or PPA and in-situ RGA and PPA calibration
techniques.

Low Concentration Humidity
Standards

OU: CSTL

Researchers: Joseph T. Hodges

Gregory E. Scace

Funding Sources: NIST OMP (75%)

Other Agency (25%)

■ Establish quantitative standards enabling the
accurate measurement of trace quantities of wa-
ter vapor (< 10 17 molecules/cm7);

■ Support the development and application of
commercial humidity sensors for gas purity
measurements.

Details of the Low Frost Point Generator (LFPG)

Laminar flow element (S,A I'ison & L. Bemdt, 1997)

Plasma Process Measurements

OU: EEEL, CSTL, PL

Researchers: James K. Olthoff

Mark Sobolewsski
Kristen Steffens
Eric Benk
L. Christophorou

Funding Sources: NIST OMP (65%)

NIST ATP (5%)

NIST SRD (5%)

NIST STRS (15%)

Other Agency (10%)

m Develop diagnostic techniques and physical
understanding of low temperature discharges
necessary for real time control and predictive
modeling of plasma etch and deposition proc-
esses;

s Develop rf-based ion-flux and ion energy
measurement technology, transfer the technology
to industrial partners, and assess its utility in
commercial plasma processes;

■ Measure composition and energies of ion
fluxes generated in reactive plasmas exposed to
semiconductor wafers;

■ Complete development of optical tomogra-
phy as a plasma uniformity diagnostic and
demonstrate performance on a commercial etch-
ing reactor.

Metrology for Contamination-Free
manufacturing

OU: CSTL

Researchers: Ronald W. Davis

Donald R. Burgess

Funding Sources: NIST OMP (100%)

■ Acquire an improved understanding of the
physics and chemistry of gas-phase-generated
microcontaminants in thermal CVD reactors;

H Develop a predictive capability for this phe-
nomenon that can be utilized to guide process
parameter selection and develop microcontami-
nation standards;

• Develop experimentally validated numerical
models for microcontaminant formation,
growth and transport in rotating disk CVD
reactors.

Gaseous Electronic Conference (GEC) cell

Temperature Sensing for Rapid
Thermal Processing

OU: PL, CSTL

Researchers: Benjamin K. Tsai

David P. DeWitt
Kenneth G. Kreider
Christopher W. Meyer

Funding Sources: NIST OMP (65%)

NIST STRS (35%)

■ Develop technologies required to enable
measurement of RTP wafer absolute tempera-
tures with uncertainties of 2 °C at 1000 °C;

■ Develop a calibration wafer using thin-film
thermocouple technology, establish procedures
for in-tool calibration of radiation thermometers,
and collaborate with the semiconductor industry
in implementing new methods for traceable tem-
perature measurement.

Rapid thermal processing thermometry
test bed

Particle Measurements in Support of
the Semiconductor Industry

OU: BFRL

Researchers: George W. Mulholland

William Pitts

Funding Sources: NIST OMP (100%)

■ Develop a facility for accurately measuring
particle size and concentration and for depositing
monosize particles on calibration artifacts with
the goal of quantifying 60 nm by 2001 and 33
urn by 2006.

Optical Scattering for Wafer Surface
Metrology

OU: PL

Researcher: Thomas A. Germer

Funding Sources: NIST OMP (60%)

NIST STRS (40%)

■ Improve understanding of the behavior of
light scattering from defects, contaminants, and
roughness needed to improve optical inspection
of wafer surfaces;

■ Develop technique of ellipsometry for defect
characterization.

Optical scatterometer system

Thin-film thermocouple test wafer

Thermophysical Property Data for
Modelling CVD Processes and for the
Calibration of Mass Flow Controllers

OU: CSTL

Researchers: Michael Moldover

John Hurley

Funding Source: NIST OMP (100%)

8 Measure the thermophysical properties of
process gases, surrogate gases, and binary mix-
tures of process and carrier gases;

■ Disseminate the results as a data base pro-
viding the heat capacity, thermal conductivity,
viscosity and the pressure-density-temperature
relation for the process gases and diffusion coef-
ficients for the gas mixtures.

Representative data. NIST speed-of-light data
for chlorine as a function of pressure on various
isotherms

Temperature (K)

Significant Accomplishments

■ Measurement of the thermophysical proper-
ties of WF6 has been completed. The
thermophysical properties of WF<„ HBr, and
BCI3, important semiconductor manufacturing
gases, have been published. These data are fun-
damental for calibrating mass flow controllers
for these gases;

■ A database of thermophysical properties of

semiconductor process gases has been con-
structed and made available to the entire
semiconductor community at

http://properties.nist.gov/semiprop;

■ Extended the light scattering analysis tech-
nique to detection of metallic particles, critically
important in semiconductor manufacturing. Used
light scattering to determine roughness scattering
from CaF2 materials being considered for deep
ultraviolet lenses at 193 nm and 157 nm.

Viscosity of gases at low density

Lithography

Task Goals

As device dimensions continue to shrink, the
wavelength of the radiation used by the lithogra-
phy exposure tools has moved into the deep
ultraviolet (DUV) spectrum. Currently exposure
tools operating at 193 nm are being introduced,
and exposure tools operating at 157 nm are in
development. Looking beyond the deep ultra-
violet, extreme ultraviolet radiation (EUV) at 13
nm is being investigated, and demonstration
tools are being designed and assembled. The
overall goal of this task is to support these de-
velopments in DUV and EUV.

Customer Needs

The semiconductor industry needs materials with
we 11 -characterized optical properties for use as
optics and masks in the DUV region of the spec-
trum. Accurate, reliable radiometers suitable for
use as wafer-plane dosimeters are needed both in
the DUV and EUV. High accuracy surface
measuring capability is needed both for EUV
mask and optics characterization. The reflectivity
of the EUV mirrors (some as large as 400 mm in
diameter) must be accurately measured as a
function of wavelength (near 13.4 nm), angle of
incidence, and position.

Technical Strategy

We have established capability for highly accu-
rate measurements in the region surrounding 157
nm of the index of refraction, dispersion, and
stress-induced birefringence of the materials to
be used for the DUV optics and mask reticles at
this wavelength. It is also necessary to be able to
accurately measure the index of refraction for
both the N2 and Ar used as purge gasses in the
157 nm DUV steppers.

In addition to the measurement capability, it is
necessary to develop DUV transfer standards to
assist the equipment vendors and process engi-
neers in qualifying the equipment and processes
used in this wavelength area.

Photodetectors and energy meters that are radia-
tion resistant are crucial for use with the DUV
excimer lasers.

We will provide leading edge metrology for the
development and characterization of optical
components and detectors to be used in EUV li-
thography.

Projects

Metrology for Deep Ultraviolet
Lithography

OU: PL, EEEL

Researchers: John H. Burnett

Rajeev Gupta
Chris Cromer
Marla Dowell
Richard Jones
Holger Laabs
Darryl Keenan

Funding Sources: NIST OMP (50%)

NIST STRS (50%)

■ Measure accurately (= ppm) the index of re-
fraction as a function of temperature, dispersion,
transmission, and stress-induced birefringence of
CaF2 and other DUV transmitting materials in
the region near 157 nm;

■ Establish calibration services for laser power
and energy meters and develop transfer standards
for pulsed laser radiometry of DUV excimer la-
sers;

■ Study 157 nm radiation damage mechanisms
of optics and detectors.

Dispersion of VUV Materials

Metrology for EUV Lithography

OU: MEL, PL

Researchers: Angela Davies

Chris Evans
Tom Lucatorto
Charles Tarrio
Keith Lykke

Funding Sources: NIST OMP (20%)

NIST STRS (80%)

“ Commission "XCALIBIR,” a unique NIST-
designed phase-measuring interferometer for
nanometer-level optical figure measurement that
will augment the present state-of-the-art figure
measuring capability and will be used for wafer
flatness and mask flatness characterization;

H Commission the large reflectometer that is
part of the NIST/DARPA EUV Optics Charac-
terization Facility. (This reflectometer is the only
one in the world capable of providing a point-by-
point map of the reflectivity for the large mirrors
to be used in EUV steppers such as the ETS Al-
pha tool presently being assembled by the EUV-
LLC.);

m Develop a calibration capability for the de-
tectors to be used as EUV wafer-plane
dosimeters.

EUV reflectometer for large lenses used in EUV
lithography tool

Significant Accomplishments

■ With funding support from SEMATECH
and OMP, completed development of a new
DUV primary standard calorimeter for measure-
ment of 193 nm excimer laser pulse energy.
Established 193 nm excimer laser power and en-
ergy meter calibration services with an expanded
uncertainty of = 1

88 Established a measurement system for the
transmittance of optical materials (e.g., fused
silica and calcium fluoride) using a 193 nm ex-
cimer laser. Measurements are performed in a
nitrogen gas environment with an uncertainty of
< 1 %, and are available to customers as a spe-
cial test;

■ Completed survey of 1 57 nm index and dis-
persion of latest grades of CaF2 from all major
suppliers, establishing a supplier index variation
of about 10 ppm. Determined that BaF2 satisfies
the criteria for second index material after com-
pleting a survey of 157 nm index and dispersion
of all candidate second index materials to be
used with the CaF2 for optics achromatization.
The survey for second index material included
BaF2, SrF2, and LiF;

H Completed initial measurements of the char-
acterization and degradation of photodiodes after
irradiation from an excimer source at 157 nm;

■ Completed the measurements of high accu-
racy transmission measurements of transmissive
materials in the spectral range from 120 nm to
300 nm;

H Established a measurement system for the
spatial characterization of excimer laser beams,
which includes the capability for performing
measurements of irradiance profiles, beam di-
vergence, M~ values, spatial uniformity, and
spatial irradiance correlations;

H Designed and constructed a measurement
system for energy density, or dose, measure-
ments using 193 nm excimer laser. Progressing
on schedule to complete characterization of this
system by the end of calendar year 2001;

“ Completed XCALIBIR installation and
made first measurements as part of the process of
commissioning.

Modeling, Design, and Test

Task Goals

Device scaling to atomic dimensions and inte-
gration of components on single chips exceeding
a billion active components requires new con-
cepts m modeling of processes, circuit
performance, and thermal management. Lead
counts of several thousand per chip and test fre-
quencies in the microwave regime challenge
current test methodologies. The overall task is to
develop modeling and test methodologies to ad-
dress these new requirements.

Customer Needs

The industry needs very efficient and reliable
simulation methods as device structures and
packages continue to rapidly evolve. Conven-
tional methods are no longer suitable and
simulators must include quantum mechanical
physics. Researchers at NIST recognize that the
most efficient and appropriate way to approach
the challenge is to work in concert with an in-
dustry consortium (Semiconductor Research
Corporation), and the National Science Founda-
tion bringing together the top people in
workshops and working groups.

Accurate at-speed test methodology of digital
integrated circuits is also a critical requirement.
Traditional methods utilizing IC contact probing
technology requires large contact pads incom-
patible with current IC designs. The
development of alternative probing approaches
through non-contact and intermittent probing
techniques appear very promising. However, to
implement these techniques, solving the at-speed
test calibration issues is crucial.

Technical Strategy

With the challenges facing designers and the
rising costs of development, it is extremely im-
portant to develop accurate testing, modeling and
simulation strategies. Keeping pace with the
technology and serving the needs of the industry
involve more than basic measurements.

Benchmarking semiconductor device simulation
tools that include quantum mechanical effects
are important facets of the overall strategy.
These software tools include MEDICI,
UTQuant, NCSU code, and NEMO, all widely
used in industry. The NIST/IEEE Model Valida-
tion Working Group continues the development
of the infrastructure necessary for validating the
performance of compact models.

The thermal performance of a system can be ac-
curately simulated through the application of the
NIST electro-thermal network simulation meth-
odology. Methodologies are being developed to
validate the performance and accuracy of com-
pact thermal models that support the shrinking
device architecture.

The development of calibration artifacts and pro-
cedures are also very important. Specifically,
calibration artifacts in the form of custom inte-
grated circuits containing special test structures
and precisely known high-frequency voltages
and circuits will be devised. Calibration proce-
dures applied to miniature AFM probes will test
both the intermittent and non-contact modes of
scanning capacitance microscopy.

Time-Domain Reflectometry (TDR) will be used
to characterize a number of multichip-module
and discrete package interconnect systems. The
calibration approaches will be verified using the
sinusoidal signals, waveform measurement capa-
bility will be developed as will pulsed versions
for calibration of the time-domain measurement
systems.

Projects

Metrology for Simulation and Com-
puter-Aided Design

At-Speed Test of Digital Integrated
Circuits

QU: EEEL

OU: EEEL

Researcher: Allen R. Hefner, Jr.

Funding Sources: NIST OMP (47%)

NIST STRS (36%)

NIST ATP (15%)

Other Agency (2%)

H Facilitate efficient and reliable application
of semiconductor CAD tools by development of
industry infrastructure for establishing model ac-
curacy, methods, and for simulator model
verification and benchmarking;

■ Develop metrology for providing model data
and model parameter extraction techniques se-
quences;

■ Develop models and techniques necessary
for advanced device process, package, and sys-
tem simulation.

Benchmarking of Quantum Mechanical Device Simulators to
Expedite Design of Deep Submicron Transistors

• Most Comprehensive Evaluation Gale Dleieclnc

and poly-Si depletion

Researchers: Dylan Williams

John Moreland
Joseph J. Kopanksi

Funding Sources: NIST OMP (100%)

■ Develop metrology for the at-speed test of
digital integrated circuits through the resolution
of the essential metrology issues;

■ Apply results to atomic force microscopes
modified to precisely position field probes above
the surface of the integrated circuit.

Integrated circuit test structure for high-speed
testing development

Formation of Dynamic Hot Spot

Significant Accomplishments

■ A new high speed transient thermal imaging
system was developed that provides the capabil-
ity to measure the transient temperature
distributions on the surface of a silicon chip with
one-microsecond time, and fifteen-micrometer
spatial resolution. The system uses virtual in-
strument graphical user interface software that
controls an infrared thermal microscope, transla-
tion stages, digitizing oscilloscope, and a device
test fixture temperature controller. The new sys-
tem is more than four orders of magnitude faster
than conventional infrared thermal imaging sys-
tems. The higher speed enables the observation
of semiconductor device dynamic failure events
and enables the localization of small heat sources
before the heat has time to diffuse to surrounding
areas;

■ Researchers in the Semiconductor Electron-
ics Division (SED) initiated a study to compare,
for the first time, quantum mechanical simulators
and analysis software suites that are critical to
the continued shrinking of silicon complemen-
tary metal oxide semiconductor (CMOS)

transistor structures. The SED's Dr. Curt Richter,
in collaboration with Drs. Allen Hefner and Eric
Vogel, presented invited summaries of these
findings to the SEMATECT1 Gate Stack Engi-
neering Working Group and the International
Metrology Council. A paper was also published
in the IEEE Electron Device Letters. As a result
of Dr. Richter's presentation on quantum me-
chanical (QM) Benchmarking, Professor John
Hauser (NCSU), who has produced one of the
more widely used QM codes, changed his simu-
lation code. Professor Hauser contacted Dr.
Richter via e-mail, stating, "Your presentation
last week prompted me to take another look at
how I have been modeling the polysilicon depic-
tion problem ... I have gone back and changed
slightly my first order model for polysilicon de-
pletion.” As an additional result of Dr. Richter's
presentation, the Lucent Technologies' electrical
characterization team in Orlando plans to acquire
and use John Hauser's revised code; the code
adjustment is already propagating into industry's
metrology practices.

Appendix A:

Index of Researchers

Allen, Richard A. 4
Benk, Eric 20
Berg, Robert 19
Bonevich, John E. 14
Burgess, Donald R. 20
Burnett. John H. 23
Chandler-Horowitz, Deane 18
Christophorou, L 20
Cresswell, Michael W. 4
Cromer, Chris 23
Dagata, John 2
Davies, Angela 19,24
Davis, Ronald W. 20
Deslattes, Richard 1 1
DeWitt, David P. 21
Dixon, Ronald G. 2
Doiron, Ted 5
Dowell, Marla 23
Drexler, Elizabeth 16
Ehrstein, Janies R. 10
Evans, Christopher 19,24
Fickett, Fred R. 14
Gaitan, Michael 15
Gayle, Frank 1 7
Germer, Thomas 2 1
Gillen, Greg 8
Gupta, Rajeev 23

Harmon, George 17
Hefner Jr., Allen R. 26
Hilton, Gene 12
Hodges, Joseph T. 19
Hurley, John 22
Irwin, Kent 12
Janezic, Michael 15
Johnson, Chris 17
Jones, Richard 23
Kaiser, Debra 1 1
Kalnas, Christine E. 14
Keenan, Darryl 23
Keller, Robert R. 14
Kelley, David 17
Kopanski. Joseph J. 7,26
Kreider, Kenneth G. 2 1
Laabs, Holger 23
Lucatorto, Tom 24
Lykke, Keith 24
Marchiando, Jay F. 7
Martinis, John 12
Maslar, James E. 1 8
Matyi. Richard 1 1
Meyer, Christopher W. 21
Moldover, Michael 22
Moreland, John 26
Mulholland, George W. 21
Nguyen, Nhan V. 10
Olthoff, James K. 20
Pitts, William 21

Postek, Michael 2,3
Potzick, James 5
Read, David 14,16
Rennex, Brian G. 7
Richter, Curt A. 10
Scace, Gregory E. 19
Schafft, Harry 14
Silver, Richard M. 4,5
Simons, David S. 8
Small, John A. 11.12
Smith, David R. 16
Snyder, Chad R. 16
Sobolewski, Mark 20
Stafford, Gery R. 14,17
Steel, Eric 1 2
Steffens, Kristen 20
Suehle, John S. 1 I
Tarrio, Charles 24
Teague, E. Clayton 19
Tsai, Benjamin K. 2 1
Vaudin, Mark 14
Villarrubia, John S. 3
Vladar, Andras 3
Vogel, Eric 10,1 I
Vorburger, Theodore 2
Williams, Dylan F. 15,26
Wollman, David 12

Appendix B:

NIST-Wide OMP Managed Projects

National Semiconductor
Metrology Program FY2001

Building and Fire Research
Laboratory (BFRL)

■ Particle Measurements in Support of the
Semiconductor Industry 865

Chemical Science and Technology
Laboratory (CSTL)

* Thin-Film Profile Measurement Methods

and Reference Materials 837

■ Chemical Characterization of Thin Films

and Particle Contaminants 837

■ Fundamental Process Control Metrology for
Gases 836

■ Low Concentration Humidity Standards 836

■ Plasma & CVD Process Measurements 836
(with EEEL81 I & PL 842)*

■ Metrology for Contamination-Free Manu-

facturing 836

■ Temperature Measurement for Rapid Ther-
mal Processing 836 (with PL 844)*

■ Thermophysical Property Data for Modeling
CVD Processes and for the Calibration of Mass
Flow Controllers 836

Electronics and Electrical Engineering
Laboratory (EEEL)

■ Linewidth and Overlay Standards for

Nanometer Metrology 812

■ Scanning Probe Microscopy for Dopant Pro-
filing 812

■ Alternate Gate Dielectric Metrology for

CMOS Technology 8 1 2

■ Thin Film Process Metrology 812

■ Ultra-Thin Dielectric Reliability Metrology
812

■ Test Structures for Mechanical Strain Char-
acterization in IC Interconnects 812

■ High-Resolution Microcalorimeter X-Ray
Spectrometer for Chemical Analysis 814

■ Interconnect Materials and Reliability Me-
trology 812 (with MSEL 853)*

■ Plasma & CVD Process Measurements
81 1( with CSTL 836 & PL842)*

■ Deep Ultraviolet Laser Metrology for Semi-
conductor Photolithography 815

■ Metrology for Simulation and Computer-
Aided Design 812

■ Thin-Film Characterization for Transmis-
sion-line Measurement 813

■ At-Speed Test of Digital Integrated Circuits
813

■ Packaging Studies (Wire Bonding to
C’u/Low k Semiconductor Devices) 812 (with
MSEL)* 855

■ Metrology for Deep Ultraviolet Lithography
815 (with PL 842 844)*

Manufacturing Engineering
Laboratory (MEL)

■ Nanometer-Scale Dimensional Metrology
with SEM and Scanned Probe Techniques 821

■ Nanometer-Scale Dimensional Metrology
with Atomic Force Microscopy 821

■ Scanning Electron Microscope Dimensional
Metrology 82 1

■ Model-Based Linewidth Metrology 821

■ High Accuracy Tow-Dimensional Metrol-
ogy 821

■ Atom-Based Dimensional metrology 821

■ Optical Overlay and CD Metrology 82 1

■ Wafer and Chuck Flatness and Thickness
822

■ Metrology for EUV Lithography 822 (with
PL 841)*

Materials Science and Engineering
Laboratory (MSEL)

a Experimental Micromechanics by e-Beam
Moire 853

m Interconnect Materials and Reliability Me-
trology 853 (with EEEL 812 )*

m Thermal Conductivity of Microelectronic
Structures 853

a Solderability Measurements for Microelec-
tronics 855

H Measurements for Electrodeposited Copper
Interconnects 855

s Packaging Studies (Wire Bonding to
Cu/Low k Semiconductor Devices) 855 (with
EEEL 812)*

Physics Laboratory (PL)

■ Plasma Process measurements 842 (with
CSTL 836 & EEEL 811)*

■ Temperature Measurement for Rapid Ther-
mal Processing 844 (with CSTL 836)*

■ Optical Scattering for Wafer Surface Me-
trology 844

■ Metrology for Deep Ultraviolet Lithography
842 844 (with EEEL 811)*

■ Metrology for EUV Lithography 841 (with
MEL 822)*

Electronics and Electrical Engineering Laboratoi

Appendix C:

Key to Funding Sources

NIST OMP:

NIST Office of Microelectronic Programs

NIST S I RS:

NIST Scientific and Technical Research and
Services

NISTSRMP:

NIST Standard Reference Material Program

NIST SRI)

NIST Standard Reference Data

NIST ATP:

NIST Advanced Technology Program

OTHER Agency:

The designation of “Other Agency” may include,
but is not limited to. International SEMATECH,
DARPA/ARPA, and the National Science
Foundation.

January 2001

For additional information contact:
Telephone: (301) 975-4400
Facsimile: (301) 975-6513
On the Web: http://www.eeel.nist.gov/omp/